1. Field of the Invention
The present invention relates to a plasma display panel, and more particularly, to a plasma display panel and driving method thereof, which controls the time data signals are applied to X electrodes during an address period, thereby reducing noise affecting waveforms that are applied to the Y electrodes and/or Z electrodes, stabilizing an address discharge, and preventing damage to the scan board and/or a sustain board.
2. Background of the Related Art
A plasma display panel includes barrier ribs formed between a front substrate and a rear substrate. Together, the barrier ribs and the front and rear substrates from cells. Each of the cells is filled with a primary discharge gas such as neon (Ne), helium (He) or a mixed gas comprising Ne and He. In addition, each cell contains an inert gas comprising a small amount of xenon.
If the inert gas is discharged using a high frequency voltage, ultraviolet rays are generated. The ultra-violet rays, which are invisible to the human eye, excite light-emitting phosphors in each cell, thus creating a visible image. Plasma display panels can be made thin and slim, and have thus been in the spotlight as the next-generation of display devices.
FIG. 1 is a perspective view illustrating the configuration of a conventional plasma display panel. As shown in FIG. 1, the plasma display panel includes a front substrate 100 that serves as the display surface on which the images are displayed, and a rear substrate 110 forming a rear surface. The front substrate 100 and the rear substrate 110 are parallel to each other, with a predetermined distance therebetween.
The front substrate 100 includes a scan electrode 101 (Y electrode) and a sustain electrode 102 (Z electrode), both of which are employed in controlling the discharge and light emission of the discharge cell shown in FIG. 1. The Y electrode 101 and the Z electrode 102 each have a transparent electrode “a” made of a transparent ITO material, and a bus electrode “b” made of a metal material. The Y electrode 101 and the Z electrode 102 together form an electrode pair. The Y electrode 101 and the Z electrode 102 are covered with at least one dielectric layer 103 for limiting a discharge current and for providing insulation. A protection layer 104, having magnesium oxide (MgO) deposited thereon to facilitate a discharge condition, is formed on the dielectric layer 103.
In the rear substrate 110, barrier ribs 111 in the form of a stripe pattern (or well type), for forming a plurality of discharge spaces, i.e., discharge cells, are arranged in a parallel manner. Further, a plurality of address electrodes 112 (X electrodes) for use in achieving an address discharge which, in turn, results in the generation of ultraviolet light, is disposed parallel to the barrier ribs 111. Red (R), green (G) and blue (B) phosphors 113, for emitting visible light for image display upon address discharge, are coated on a top surface of the rear substrate 110. A white dielectric layer 114, which protects the address electrodes 112 and reflects the visible light emitted from the phosphors 113 to the front substrate 100, is formed generally between the address electrodes 112 and the phosphors 113.
The plasma display panel constructed above includes a plurality of discharge cells in the form of a matrix, and a driving module having a driving circuit for supplying a given driving signal to the discharge cells. The coupling relation between the plasma display panel and the driving module will be described with reference to FIG. 2.
FIG. 2 illustrates the coupling relation between the plasma display panel 22 and the driving module. As shown, the driving module can include a data driver integrated circuit (IC) 20, a scan driver IC 21, and a sustain board 23.
The plasma display panel 22 receives an image signal from the outside, a data signal, which has undergone predetermined signal processing by the data driver IC 20, a scan signal from the scan driver IC 21, and a sustain signal output from the sustain board 23. Discharge occurs in selected cells, which are selected from among the plurality of cells in the plasma display panel 22 that have received the data signal, the scan signal, the sustain signal, and the like. In cells where discharge has occurred, light is emitted at a predetermined brightness.
FIG. 3 illustrates a method for implementing a gray scale image in a conventional plasma display panel 22. As shown, in order to provide a gray scale image in the conventional plasma display panel, each image frame is divided into a plurality of sub-fields, where each sub-field has a different number of emission. Each sub-field is subdivided into a reset period RPD for initializing all of the discharge cells, an address period APD for selecting a number of the discharge cells, and a sustain period SPD for implementing the gray scale according to the number of discharges. For example, if it is desired to display an image with 256 gray scales, a frame period (16.67 ms) corresponding to 1/60 of a second is divided into eight sub-fields SF1 to SF8, as shown in FIG. 3. Again, each of the eight sub-fields SF1 to SF8 is subdivided into a reset period, an address period and a sustain period.
The time period associated with the reset period and the address period of each sub-field is the same for every sub-field. The address discharge which results in the selection of certain cells is generated by establishing a voltage difference between the X electrodes and transparent Y electrodes corresponding to those cells, where Y electrodes refer to the scan electrodes and the X electrodes refer to the address electrodes.
The time period and the number of sustain pulses that are associated with the sustain periods increase by a ratio of 2n (where, n=0, 1, 2, 3, 4, 5, 6, 7) for each sub-field SF1 to SF8, as shown in FIG. 3. As such, since the sustain period varies from one sub-field to the next, the gray scale of an image is achieved by controlling which sustain periods are to be used for discharging each of the selected cells, i.e., the number of the sustain discharges that are realized in each of the discharge cells. A driving waveform for use in a method of driving the plasma display panel will now be described with reference to FIG. 4.
FIG. 4 illustrates a driving waveform that is used for driving a plasma display panel in accordance with the prior art. As shown, during a given sub-field, the waveforms associated with the X, Y and Z electrodes are divided into a reset period for initializing all cell, an address period for selecting cells that are to be discharged, a sustain period for maintaining discharging of selected cells, and an erase period for erasing wall charges within each of the discharge cells.
During a set-up period of the reset period, a ramp-up waveform (Ramp-up) is applied to all of the Y electrodes at the same time. As a result, weak dark discharge is generated in all of the discharge cells for the entire screen. It will be understood that the term “dark discharge” refers to a discharge within a given cell that results in little or no visible light emission. The set-up discharge causes wall charges of a positive polarity to be accumulated at the X electrodes and the Z electrodes, and wall charges of a negative polarity to accumulate at the Y electrodes, where the Z electrodes refer to the sustain electrodes.
During a set-down period, after the ramp-up waveform is supplied, a ramp-down waveform (Ramp-down), which falls from a positive polarity voltage lower than the peak voltage of the ramp-up waveform, to a given voltage lower than a ground GND level voltage. This causes a weak erase discharge to occur in all of the cells. Therefore, excessive wall charges formed on the Y electrodes are sufficiently erased. The set-down discharge also optimizes the wall charges for the address period, such than an address discharge can be generated stably within the appropriate cells.
During the address period, while a negative scan signal (Scan) is sequentially applied to the Y electrodes, a positive data signal is applied to the X electrodes in synchronism with the scan signal. As a result of the voltage difference between the scan signal and the data signal, as well as the wall voltage generated during the reset period, an address discharge is generated within those discharge cells to which a data signal is applied. Furthermore, wall charges, sufficient for generating a discharge when a sustain voltage Vs is applied, are formed within cells selected by the address discharge. A positive polarity voltage Vz is applied to the Z electrodes so that erroneous discharge does not occur with the Y electrode by reducing the voltage difference between the Z electrode and the Y electrode during the set-down period and the address period.
During the sustain period, a sustain signal (Sus) is alternately applied to the Y electrodes and the Z electrodes. In cells selected during the address period, a sustain discharge, i.e., a display discharge, is generated between the Y electrodes and the Z electrodes whenever the sustain signal is applied.
After the sustain period is completed, there is an erase period, during which a voltage associated with an erase ramp waveform (Ramp-ers), which has a small pulse width and a low voltage level, is applied to the Z electrodes, so that wall charges remaining within all of the cells are erased.
In a plasma display panel driven with the driving waveform of FIG. 4, when the data signal is applied to the X electrodes during the address period, the data signal is applied to all of the X electrodes X1 to Xn at the same time. The point in time that the data signal is applied during the address period in accordance with the prior art, will now be described with reference to FIG. 5.
FIG. 5 is a conceptual view that illustrates the point in time the data signal is applied in a conventional plasma display panel. As shown in FIG. 5, in the conventional plasma display panel, the data signal is applied to all the X electrodes X1 to Xn at the same time point t0. This introduces noise which affects the waveform applied to the Y electrodes as well as the waveform applied to the Z electrodes. An example where such noise is affecting the waveform applied to the Y electrodes and the waveform applied to the Z electrodes, when a corresponding data signal is applied to all of the X electrodes X1 to Xn at the same time, is described below described with reference to FIG. 6.
FIG. 6 illustrates the noise that may be associated with the waveforms applied to the Y electrodes and the Z electrodes due to the data signal applied to the X electrodes in a conventional plasma display panel. Referring to FIG. 6, in a conventional plasma display panel, if the data signal is applied to all the X electrodes at the same time during the address period, noise is generated which may affect the waveforms applied to the Y electrodes and the Z electrodes. This noise is generated due to coupling capacitance. Mores specifically, when the data signal abruptly rises, a rising amount of noise on the waveforms applied to the Y electrodes and the Z electrodes can be observed. When the data signal abruptly falls, a decreasing level of noise on the waveforms applied to the Y electrodes and the Z electrodes can be observed.
As described above, the noise may affect the waveforms applied to the Y electrodes and the Z electrodes due to the data signal being applied to the X electrodes at the same time, makes the address discharge unstable, thereby degrading driving efficiency of the plasma display panel. Furthermore, it can seriously damage the scan board and/or the sustain board in the driving module.